Particular embodiments generally relate to reference generators.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
High-speed data converters use internal reference buffers to provide references. For example, the references may be provided to an analog to digital converter (ADC). FIG. 1 shows a conventional voltage reference buffer. Transistors M1 and M2 share a same current Id1 to generate output voltages Vrp and Vrn. The gate voltages Vg1 and Vg2 of transistors M1 and M2, respectively, are biased by a replica circuit (e.g., a transistor M3, a resistor R2, and a transistor M4) such that output voltage Vrp is set at 1.3V and output voltage Vrn is set at 0.3V.
A resistor R1 is adjusted to establish current Id1 as (voltage Vrp−voltage Vrn)/resistance R1, where current Id1 is directly related to the noise performance of the reference buffer. In operation, the voltage Vrp will go down at a moment when the reference voltage buffer is switched to sampling capacitors of the ADC. At this time, the current going through transistor M1 increases and the equivalent output impedance drops to help bring voltage Vrp up. The mechanism for the negative output voltage Vrn is the same, except that the swing direction is in the opposite direction.
In some cases, gate voltages Vg1 and Vg2 may need to go beyond power supply voltages of Vdd and Vss because of the voltage levels of output voltages Vrp and Vrn, respectively. For example, gate voltage Vg1 needs to be above the output voltage Vrp plus the threshold voltage of transistor M1 and gate voltage Vg2 needs to be below the output voltage Vrn plus the threshold voltage of transistor M2.
Positive and negative boosted voltages Vdd2 and Vss2 are generated to overcome the above problem. Voltages Vdd2 and Vss2 are used to supply the minimum required currents to set up the desired voltages Vg1 and Vg2. Voltages Vdd2 and Vss2 may be generated on an integrated circuit (IC) chip that includes the voltage reference buffer. For example, a charge pump that includes a flying capacitor may be used to generate voltages Vdd2 and Vss2. In this case, the flying capacitor takes up area on the chip.
Also, the current through transistors M5 and M8 may be about 100-200 μA. The current is delivered by the on-chip charge pump, which requires a certain size of flying capacitor. This increases the area used and also power consumption. A power supply ripple is also introduced that may reduce the accuracy of the voltage reference buffer.
FIG. 2 depicts a second conventional voltage reference buffer 200. Reference buffer 200 uses two positive supply reference voltages Vdd1 and Vdd2, and one ground voltage Vss. The negative reference voltage Srefn is delivered by a constant current sink. Bias currents through first and second transistor followers 25 and 26 are provided by first and second current transistors 29 and 30 in response to a bias voltage Vb. Transistor followers 25 and 26 convert first and second voltage signals at the gates of transistor followers 25 and 26 to first and second reference signals Srefp and Srefn.
When reference buffer 200 is coupled to dynamic charge sampling capacitors of an ADC, a transient voltage at voltage Srefn goes up at the moment when reference buffer 200 is switched to the sampling capacitors. Voltage Srefn is then pulled down by the constant current sink of transistor 30, and not by positive feedback mechanism. Thus, the settling speed of voltage Srefn is limited by the constant current sink. Further, because the current sink through transistor 30 is constant, the constant current needs to be high such that enough current can be sinked to increase voltage Srefn. This increases the power used and also limits the amount of current that can be sunk. Also, a charge pump may be needed to generate the boosted positive supply voltage Vdd1, which increases the area used on the chip as described above.